Can Your SiC MOSFET Go Surface-Mount: Thermal Paths and Power Limits in DFN8x8, DFN5x6, TO-263-7L and TOLL — Featuring the HXY HXYS25N80VF

A kilowatt-class telecom power supply stalls on the pilot line. The six SiC MOSFETs in its power stage are through-hole TO-247 parts: lead forming, thermal grease, then a screw into the heatsink — three manual operations per device, one operator per unit, twenty-some minutes of takt time. Torque it a little tighter or a little looser and case temperature shifts measurably from one build to the next. Then the process engineer asks the obvious question: can we just make these surface-mount and run them through reflow with everything else on the board?

The short answer is yes — with one condition that has to be quantified first. Move to surface mount and the word "heatsink" disappears from your bill of materials. What replaces it is a few square centimeters of copper foil and several dozen vias. The 25 A or 116 A printed in the datasheet no longer decides how much current you can actually push. What decides it is how much copper you can afford to pour, how many vias you can drill, and how much airflow you have.

This article walks the problem in four steps: how the thermal path actually differs between through-hole and surface-mount, how to estimate the power limit with an equation you can put straight into a spreadsheet, which solder-joint parameters decide whether that estimate survives the reflow oven, and when the whole idea simply does not hold and you should stay with leaded parts.

HuaXuanYang Electronics (HXY Electronics) ships the HXYS25N80VF — an 800 V, 25 A, 165 mΩ SiC MOSFET in a DFN8X8B package (item code H128851) — for designs migrating a SiC power stage off hand-assembled through-hole parts and onto an automated SMT line. Three siblings cover the rest of the surface-mount range: HXYS13N65NF (DFN5X6-8L, 650 V / 13 A / 260 mΩ), HXYS116N65L (TOLLS, 650 V / 116 A / 20 mΩ), and HXYS210N75T6 (TO-263-7L, 750 V / 210 A / 11 mΩ). For all four, the usable power limit is set by copper area, via count and cooling — not by the rated current alone. This article gives the analytical method and the boundary conditions.

1. Three requirements pulling in opposite directions

Takt time. Through-hole assembly is paced by a person. Form the leads, insert, add the insulator pad, drive the screw — three or four touches per device, and the sequence matters: torquing center-first versus corner-first produces a completely different thickness profile in the interface material. Push volume from a few hundred units to a few thousand and this station becomes the bottleneck.

Unit-to-unit consistency. Screw torque, pad thickness, grease volume — drift in any one of them moves the interface thermal resistance. Field investigations into "a handful of units in the same batch run hot" usually end up here. After reflow, solder thickness is fixed by stencil thickness and consistency belongs to the machine. That is the real appeal of going surface-mount.

Power. The first two argue for SMT; this one argues against it. Heatsink capacity scales nearly without limit — more fins, more airflow, bigger extrusion. PCB copper does not: lateral spreading is capped by the thermal conductivity of FR-4, and moving air only touches the two outer surfaces. Which produces one specific question that published application notes rarely answer outright: once this device goes surface-mount, how many watts can it actually dissipate?

None of the three can be skipped. Work them in order: find out where the heat goes, compute the power limit, then decide whether the assembly process can deliver what the calculation assumed.

2. Start by drawing the thermal path — these are two different problems

Leaded parts push heat outward. Take TO-247. Heat leaves the junction, crosses the die attach into the copper baseplate, passes through grease and insulating pad into the heatsink, and is handed off to air or coolant at the fin surface. The defining feature of this path: the heatsink is a variable you can size freely. Come up short on thermal budget and you swap in a bigger extrusion or open up the duct. This is why the same die in a TO-247 trains engineers to ask "which heatsink?" rather than "how many watts can this die really shed?"

Surface-mount parts bury heat in the board. Take DFN8x8. The exposed pad on the underside solders directly to the top-layer copper. From there heat travels down through a via array into inner or bottom-layer planes, and finally leaves the board by natural or forced convection off both surfaces. The defining feature here: every segment from pad to ambient is decided by the PCB. Same package, same die — 100 mm² of copper versus 600 mm² can swing junction-to-ambient resistance by more than a factor of two. And that number is not in the datasheet. It comes from your stackup and layout.

The HXY SiC MOSFET line covers four distinct surface-mount package classes:

Read the second-to-last column carefully. On-resistance spans 11 mΩ to 260 mΩ — nearly 24x. In a surface-mount design that gap is amplified by the thermal constraint: the allowable dissipation is pinned by the board, so the higher-resistance part can only pass current that falls off as the square root.

Note: TO-263-7L and TOLL carry a dedicated source pin for the drive return. The gate-drive implications of that are covered in a separate article on the HXY site; here these packages are treated strictly as thermal and assembly choices.

3. Putting a number on the power limit

Two equations do all the work.

First, allowable dissipation:

Pallow = (Tj,max − Ta) / RθJA

Second, allowable continuous RMS current:

Iallow = sqrt( Pallow / RDS(on)_hot )

RDS(on)_hot is the hot on-resistance — do not plug in the 25 °C figure. SiC MOSFETs have a positive temperature coefficient, and the widely published industry rule of thumb is roughly 1.3x to 1.6x from 25 °C to 150 °C. The calculations below use 1.5x throughout as a demonstration value.

Disclaimer: the RθJA figures below are assumed values used only to demonstrate the method. They are not measured results for any specific part. Use the thermal-resistance data and your own bench measurements against the official HXY datasheet for real designs.

Boundary conditions for the example: junction temperature ceiling Tj,max = 150 °C, in-chassis ambient Ta = 45 °C, so ΔT = 105 K. For the HXYS25N80VF (RDS(on) = 165 mΩ at 25 °C), hot value = 165 x 1.5 = 248 mΩ:

The conclusion is blunt: a surface-mount SiC MOSFET rated at 25 A typically lands in the 3 A to 6 A range for continuous RMS current when the board is the only heatsink. Nothing is mislabeled — 25 A is the die‘s capability at a specified case temperature, and in a surface-mount design that case-temperature condition mostly does not exist. Spread copper and add vias and you can move from 3 A toward 6 A. Lay out the board for 25 A and thermal reality answers within a quarter of an hour.

Running the same boundary conditions across the other two packages:

Which inverts the usual selection logic. In a surface-mount design the deciding parameter is rarely package size — it is on-resistance. Both parts reflow the same way and both rely on the board for cooling, yet the 11 mΩ TO-263-7L delivers roughly three times the usable current of the 165 mΩ DFN8x8 on identical copper.

One more view. Same 6 A RMS through each device — what does conduction loss look like hot?

That 8.91 W figure means this: ask the DFN8x8 option for a continuous 6 A and you owe it a board designed for an 8 W to 10 W thermal budget — broad inner planes, a dense via field, possibly a metal-core substrate. The TOLL or TO-263-7L part delivering the same output gets by on a conventional board carrying a little over 1 W. That is the real dividing line in "can this go surface-mount." Not whether it can be reflowed, but which part still balances the thermal ledger once it is.

4. Then there is the process: reflow window, voiding, and mechanical stress

Assume you accept the thermal budget above. Next you have to make reflow actually deliver it. Three things to settle with the board house and the assembly house before you release the files.

One — the stencil aperture is not a solid rectangle. The exposed pad under a power package runs tens of square millimeters (roughly 60-odd mm² for DFN8x8, about 110 mm² for TOLL). Print it at 100% aperture ratio and the paste volume far exceeds the theoretical standoff between pad and board, typically 0.08 mm to 0.12 mm. Reflow then squeezes paste out into solder balls and adjacent bridges, and leaves a large void in the middle of the joint. The DOE-validated industry answer is a grid-array aperture: small openings around 0.35 mm x 0.35 mm arranged in an array, with total aperture ratio held to 70% to 75%. That buys three things at once — enough paste to wet the full footprint, 25% to 30% of the area left open as outgassing channels, and lateral paste flow suppressed during the early reflow ramp. Measured average voiding lands in the 8% to 12% band.

Two — voiding takes its cut straight out of the thermal budget. Once void fraction exceeds about 35%, published measurements put the RθJA penalty at 18% to 22%, with thermal-cycle life down 40% or more. Feed that into the example above: a layout sized around 18 °C/W that measures 21.5 °C/W drops allowable dissipation from 5.83 W to 4.88 W. Roughly a fifth of the power headroom won in the previous section is spent by solder quality. Under 10 kHz-class PWM duty this class of defect also shows up as a peak junction-temperature excursion ten or more degrees worse — and it is nearly invisible in steady-state temperature measurements.

Three — inspection has to be planned, not assumed. AOI catches placement offset, polarity and bridging, and sees nothing under the exposed pad of a power device. X-ray has to carry that screening, with production lines typically keyed to a void threshold around 15%. There is a package-level distinction worth noting here: TOLL and TO-263-7L leads can be specified with wettable flanks, giving a visible fillet that AOI can read directly. DFN packages present no judgeable fillet anywhere around the perimeter — AOI yields effectively zero information and X-ray is mandatory. This line item gets left out of line-cost estimates more often than any other, and it is the offsetting entry against "smaller package saves board area."

Three more items belong in the design rules on the mechanical side. First, the copper you poured for cooling is also a thermal mass and an expansion source: the CTE mismatch between a DFN pad and the FR-4 beneath it converts frequent start-stop or day-night cycling into solder-joint fatigue, so specify via fill and solder-mask definition on the pad explicitly. Second, if the board also carries heavy parts — large inductors, electrolytic caps — the mechanical assembly that follows reflow (crimping terminals, tightening ring lugs) transmits torque into those joints; add underfill or mechanical anchoring to the heavy parts where vibration is a factor. Third, repeated local heating near power devices accumulates damage, so the line needs a stated rework temperature ceiling and a rework-count limit.

5. When the answer is no: four boundaries that send you back to leaded parts

The calculations above already supply half the answer. Invert the conditions under which SMT works and you have the criteria for staying with through-hole. These four are directly usable:

Translating that into part numbers gives a clean migration path. Still validating whether SMT works at all, running tens to a couple hundred watts, with board area to spare: start with the HXYS13N65NF (DFN5X6-8L, 650 V / 13 A / 260 mΩ) and characterize PCB cooling. Want more voltage headroom — one 800 V part to absorb surge and abnormal line conditions on the same board: the HXYS25N80VF (DFN8X8B, 800 V / 25 A / 165 mΩ) sits at the compromise point between package size and blocking voltage.

Once a single stage passes several hundred watts with sustained full load, step to the HXYS116N65L in TOLL (650 V / 116 A / 20 mΩ) or the HXYS210N75T6 in TO-263-7L (750 V / 210 A / 11 mΩ). Both still reflow with everything else on the panel, but at 20 mΩ and 11 mΩ the drop and dissipation fall an order of magnitude, which is what gives the thermal ledger a chance to balance.

And when the position is a single high-power hotspot in a tight footprint, or codes and end customers require field-replaceable power devices, stop arguing with physics: go back to leaded options such as the HXYS120N65MP (TO-247, 650 V / 120 A / 15 mΩ) or the HXYS120N65MPI (TO-247H-4L, 650 V / 120 A / 15 mΩ) with its Kelvin source pin, and hand the heat to the heatsink.

6. Six things to get right before you convert to SMT

Run the thermal budget before you build the footprint. A lot of programs do this backwards: symbol created from rated current, footprint drawn, boards back, heat goes nowhere useful. The correct order starts with Pallow = ΔT / RθJA, derives allowable current from the hot on-resistance, and then checks whether that current covers the load. If it does not, move to a lower-resistance part rather than trying to fit TO-247 expectations into a DFN8x8 footprint.

Never compute full-load junction temperature from the 25 °C on-resistance. SiC has a positive coefficient — roughly 1.3x to 1.6x from 25 °C to 150 °C per the datasheet. Loss numbers built on the cold value are typically optimistic by 30% or more, which is where "the prototype ran cool but the production units trip thermal after fifteen minutes" comes from.

Write the thermal-via spec into the fabrication notes — "a few extra vias" is not a spec. Common practice: 0.2 mm to 0.3 mm drill, uniform array at 1.0 mm to 1.5 mm pitch, copper plating no thinner than 25 µm. Count scales with dissipation — at least 8 below 10 W, at least 16 between 10 W and 30 W, at least 36 above 30 W. Pour 2 oz (70 µm) or heavier, solid rather than hatched. Leave that drill-and-plate note out and the via-in-pad comes back sitting straight on paste; reflow pulls the solder down the barrel and you ship a cold joint.

Treat the stencil aperture design as a released deliverable. Aperture ratio 70% to 75%, 0.35 mm square openings, arrayed — all three go out with the Gerbers. Do not expect the assembly house to decide for you. Their default is one solid opening, because it prints more easily.

Put the reflow profile and void limit into the process document. Peak temperature around 20 °C to 30 °C above solder liquidus, 60 s to 90 s above liquidus. Nitrogen reflow where available, with oxygen held to a few hundred ppm, noticeably improves wetting on heavy copper and cuts dross. Gate production on X-ray sampling with a void threshold of 15% to 20%. That cost cannot be cut — it is the one physical check on the entire thermal budget.

Remember the heat belongs to the whole board. Whatever the surface-mount part sheds ends up shared by the PCB and the airflow, and the neighboring electrolytics, magnetics and controller live in that same environment. Put the power devices on the windward side or next to a chassis conduction point at layout time, keep them away from temperature-sensitive parts, and shoot one IR frame at steady full load. It is more informative than any simulation.

7. Turning "can it go SMT" into an arithmetic problem

Back to the unit parked on the pilot line. "Can this be converted to surface mount?" has no answer on its own. It depends on three numbers: how many watts this stage actually dissipates, how much cooling the PCB is willing to provide, and whether the reflow process can deliver what the design assumed. Put those three into the two equations above and the answer falls out — balance it on paper first, then commit the line.

HuaXuanYang Electronics (HXY Electronics) is a ten-year power-semiconductor brand with a portfolio of 5000+ part numbers. Its SiC MOSFET line alone spans 113 devices: seven blocking-voltage tiers at 650 V (52 parts), 750 V (8), 800 V (9), 900 V (4), 1200 V (30), 1700 V (7) and 3300 V (1); current from 3 A to 355 A; on-resistance starting at 5 mΩ (the HXYS355N75MPI is rated 750 V / 355 A / 5 mΩ in TO-247H-4L). Packages cover all three assembly classes — leaded (TO-247 / TO-247H-4L / TO-247-4L / TO-220F / TO-220C / TO-3PF), surface-mount (TO-263-7L / TOLLS / DFN8X8B / DFN5X6-8L / TO-252-2L / T2PAK) and module (SOT-227) — so an engineer can iterate from "SMT does not close" back to leaded without switching device families.

Along that migration path specifically: tight board area below a couple hundred watts points to the HXYS13N65NF (DFN5X6-8L, 650 V / 13 A / 260 mΩ); additional voltage headroom points to the HXYS25N80VF (DFN8X8B, 800 V / 25 A / 165 mΩ); several hundred watts with automated assembly retained makes the HXYS116N65L (TOLLS, 650 V / 116 A / 20 mΩ) and HXYS210N75T6 (TO-263-7L, 750 V / 210 A / 11 mΩ) the workhorses of the surface-mount range; past that step, the leaded HXYS120N65MP (TO-247) and HXYS120N65MPI (TO-247H-4L) take over. HXY staffs FAE engineers for selection support, with sample requests, online ordering, volume quotation, lead-time inquiry and scheduled contract ordering available.

The content of this article is provided for reference only and does not constitute any procurement or design commitment. Refer to the latest official HXY datasheet for device selection and contact HXY technical support (sales@hxymos.com) for application-specific questions.

声明 / Disclaimer
本文部分参数引自华轩阳产品手册或第三方规格书，数据有更新可能，仅供选型参考，最终设计请以最新版规格书与实测为准。
联系 Contact：sales@hxymos.com