A 3.3 V STM32 or ESP32 needs to read a 5 V sensor module. Or a 5 V Arduino needs to drive a 3.3 V OLED. For many engineers the first instinct is "the levels differ — just add a resistor divider." The bus then either garbles every transaction or never acknowledges, and in the worst case the low-voltage chip‘s I/O ends up latched up. I²C is a bidirectional, open-drain bus, and level shifting on it follows rules of its own. This article starts from the nature of the bus itself, breaks down how a small-signal N-MOSFET (using the BSS138 from HXY Electronics as an example: SOT-23 / 50 V / 0.2 A / 1.1 Ω) performs bidirectional level translation, and closes with a checklist of field-proven pitfalls.

1. Why level mismatch is a hard problem on I²C: the bus architecture leaves no easy way out

I²C carries all traffic on two lines (SDA for data, SCL for clock) yet can host dozens of devices, thanks to two design decisions: open-drain outputs and bidirectional half-duplex operation. No device ever drives a line high. Each device either pulls a line low or releases it, and the high level is provided by pull-up resistors tied to the local supply rail. The slave‘s mandatory ACK bit — pulling SDA low during the ninth clock — means the bus is inherently bidirectional.

That architecture produces three linked problems whenever a 3.3 V domain meets a 5 V domain:

First, there is no "middle ground" high level. Connect a 3.3 V device to a bus pulled up to 5 V and the idle high level is dragged toward 5 V, beyond the absolute maximum rating of the 3.3 V I/O. If the I/O‘s internal ESD diode conducts first, current leaks into the 3.3 V rail — at best logic misreads, at worst latch-up. When the module board carries its own 5 V pull-up, it forms a divider with the master‘s internal weak pull-up (tens of kilohms), parking the high level in a gray zone above roughly 3.6 V — timing and levels fail together.

Second, a resistor divider only steps down, and only one way. A divider maps the 5 V high level into a readable 3.3 V level, which looks fine for "master reads slave." But the ACK must travel the other way: the slave pulls SDA low, and the divider attenuates that pull-down equally. The low-voltage master never sees a valid low, and the symptom is the classic "commands go out, reads time out."

Third, direction-pinned buffers conflict with the bus. A translator with a fixed direction needs a direction-control signal, yet on I²C every line changes direction every few clock cycles (master transmits, slave transmits, ACK reverses again) — there is no way to fix the direction in hardware. Auto-direction buffers (the TXB family) detect edges to switch direction, and the pull-ups of an open-drain bus interfere with that detection; several vendors explicitly advise against using those parts on open-drain signals.

The conclusion: I²C level shifting must be directionless, passive and bidirectional. That is exactly why the Philips (now NXP) application notes AN97055/AN10441 proposed a discrete-MOSFET solution decades ago — and why it is still the default circuit on level-shifter breakout boards today.

2. The classic circuit: one N-MOSFET plus two pull-ups, and why it is bidirectional

NXP AN10441, "Level shifting techniques in I²C-bus design," describes a remarkably simple circuit: one N-channel enhancement MOSFET per bus line (SDA and SCL), with a pull-up resistor on each side of each line. The wiring orientation is a hard rule — reverse it and the circuit never works:

• Gate (G) connects to the low-voltage supply (3.3 V in this example);
• Source (S) connects to the low-voltage bus (the 3.3 V SDA/SCL);
• Drain (D) connects to the high-voltage bus (the 5 V SDA/SCL);
• Each side is pulled up to its own rail; the two domains share a common ground.

Three operating states cover one complete transaction:

State one: bus idle. No device is pulling low. The 3.3 V side rises to 3.3 V through its pull-up. Gate and source now sit at the same potential, so VGS is zero — below threshold — and the MOSFET is off. The 5 V side is pulled independently to 5 V by its own pull-up. Both sides are high, but each at its own level, without interference.

State two: a low-voltage (3.3 V) device pulls low. The source drops toward 0 V while the gate stays fixed at 3.3 V, so VGS jumps to roughly 3.3 V — far above threshold. The channel turns on and drags the drain-side (5 V) bus low. The low level propagates from the 3.3 V side to the 5 V side.

State three: a high-voltage (5 V) device pulls low first. The drain drops toward 0 V, below the 3.3 V source. The MOSFET‘s parasitic body diode (which conducts from source to drain) turns on first and pulls the 3.3 V side down by roughly one diode drop; as the source falls, VGS rises above threshold and the channel takes over, pulling the 3.3 V side fully low. The body diode only "starts" the transition — once the channel conducts it carries the current. That brief body-diode conduction is a deliberate part of the bidirectional mechanism, not a flaw.

The rule across all three states is simple: whichever side pulls low first, the low level reaches the other side; each side restores its own high level through its own pull-up. Direction sensing happens automatically, with no control signal. After release, the rising edge is set by the RC formed by the pull-up and the bus capacitance — the MOSFET contributes nothing to the rise — and that is what defines the circuit‘s speed ceiling, discussed below.

3. Why the BSS138: a small-signal MOSFET‘s parameter view

The circuit‘s demands on the MOSFET are modest, but a few parameters are hard gates, and the BSS138 clears all of them — which is why it has become the de facto standard part for this circuit (most open-source level-shifter modules and sensor breakouts use it). Taking the values from the HXY Electronics product list:

One point deserves emphasis: on-resistance is deliberately unimportant in this circuit. Engineers trained on power MOSFETs instinctively hunt for milliohm-class RDS(on), but a level shifter carries only milliamps. Drop equals current times resistance; milliamps times ohms is still millivolts, nowhere near the I²C low-level specification. A "humble" small-signal part like the BSS138 is actually the better fit: small gate capacitance, fast switching, tiny package, negligible cost. The lesson from our previous article on reading MOSFET datasheets applies here too — RDS(on) means nothing without its test conditions. The listed value is normally measured at VGS = 10 V, while this circuit drives the gate with only 3.3 V, so the real on-resistance will be higher than the headline number — and, as calculated above, it does not matter for function.

For designs that need both lines handled by one part, HXY Electronics also offers the dual-channel BSS138DW (SOT-363, two independent N-MOSFETs in one package): one half for SDA, one for SCL — less board area than two SOT-23 parts and a single part number to manage. Together the two part numbers cover both the single-line DIY build and the dual-line production route.

A common question follows: if only milliamps flow, why not grab any power MOSFET? It would work, but it is the wrong tool. Power MOSFETs are designed around 10 V-class gate drive (threshold typically 2-4 V), so a 3.3 V gate gives incomplete enhancement and an on-resistance far from the datasheet number; meanwhile the large die‘s gate capacitance, package size and cost are all wasted on one signal line. Level shifting wants a small-signal part built for low-voltage logic drive — low VGS(th), low gate charge, SOT-23-scale package. The BSS138 family is exactly that.

4. Building the full 3.3 V-master / 5 V-slave chain: pull-ups, speed, and boundaries

In a real system the signal chain reads: the 3.3 V master‘s I²C peripheral (open-drain) → 3.3 V-side pull-up → the two channels of a BSS138DW (one for SDA, one for SCL) → 5 V-side pull-up → the 5 V slave module (e.g. a sensor board with its own 5 V pull-up). The master needs no direction pin and no extra driver; its I²C peripheral works as-is, and the slave sees a standard I²C waveform.

Three design parameters are settled on site:

Pull-up resistor value. Two constraints bracket the working range. The lower bound comes from the devices‘ sink capability: Fast-mode I²C devices must sink 3 mA-class current, and too small a resistor raises the low level or exceeds that rating — stay above roughly 1 kΩ in practice. The upper bound comes from the rise-time budget: estimate with tr ≈ 0.85 × Rp × Cb and compare against the mode limits (1000 ns for Standard-mode, 300 ns for Fast-mode). A concrete example: at 400 kbit/s with about 150 pF of measured bus capacitance, the 300 ns budget caps Rp at roughly 2.4 kΩ, so take the standard 2.2 kΩ value — then verify sink current: about 2.1 mA on the 5 V side ((5 − 0.4)/2.2 kΩ) and 1.3 mA on the 3.3 V side ((3.3 − 0.4)/2.2 kΩ), both inside the 3 mA-class IOL of typical parts. On a lightly loaded bus (tens of picofarads) running 100 kbit/s, 10 kΩ is a fine, power-saving default; go tighter only when the bus is heavy or fast. Do not rely on the MCU‘s internal weak pull-ups — edges get slow enough to time out when temperature rises.

Speed ceiling. NXP‘s documentation positions this circuit for Standard-mode (100 kbit/s) and Fast-mode (400 kbit/s) and states it is not intended for 3.4 Mbit/s Hs-mode. Fast-mode Plus (1 MHz) can be reached in practice on light buses, but the rise-time margin is thin and degrades quickly as traces lengthen or devices are added. At 1 MHz and above, on long buses, or with many slaves, move to a dedicated translator such as the PCA9306 (passive switch type) or the TXS family (open-drain compatible).

Signal types. The circuit is designed for open-drain / open-collector buses: I²C, SMBus and 1-Wire all qualify. Push-pull signals (SPI, a UART TX line) do not: the MOSFET only assists pull-down and never helps pull-up, so a push-pull driver fights the circuit and distorts the waveform. Those signals belong to direction-pinned push-pull buffers.

5. Pitfall checklist: six lessons from real boards

① Reversing the low and high sides means the circuit never works. Gate must go to the low supply, source to the low bus, drain to the high bus. Reversed, VGS can never be established correctly, and the body diode may back-drive the supply. This is the first thing to check when debugging.

② Both sides need their own pull-up. With only one side pulled up, the other side floats — the MOSFET is off when idle and cannot "carry" a high level across. Highs are produced by each side‘s own pull-up, nothing else.

③ Do not let the weak internal pull-up take the blame. MCU internal pull-ups are usually tens of kilohms; alone they slow the edges, and in parallel with an external resistor they lower the equivalent value and raise sink current beyond the device‘s IOL. Disable internal pull-ups and use one deliberate external resistor per side.

④ Tie the gate only to the low-voltage rail. If the gate is left floating or tied somewhere else, VGS loses its reference and the device may conduct when idle, shorting the two buses together.

⑤ Be cautious below about 2.5 V on the low side. At a 1.8 V gate, if the part‘s VGS(th) maximum approaches or exceeds 1.8 V, some lots cannot be guaranteed to turn on. Below 2.5 V low-side, check the VGS(th) maximum in the datasheet — and when in doubt, use a dedicated translator IC. This is also why you should confirm the logic-level grade with the supplier when selecting parts.

⑥ Do not use this circuit for push-pull signals. To repeat: it is the open-drain bus solution. For SPI or UART TX, use a direction-pinned buffer (74LVC family) or an auto-direction part that supports push-pull — do not reuse an I²C level-shifter board.

6. Manufacturer‘s note and summary

The right way to level-shift I²C, in one sentence: use a low-threshold N-MOSFET as a directionless bidirectional switch and let the open-drain logic do the level negotiation itself. The BSS138 became the industry default for this circuit not because its numbers are spectacular, but because every parameter lands exactly where the circuit needs it — low-voltage turn-on, milliampere currents, millivolt drops, SOT-23 SMD, negligible cost. When both lines should be covered by a single part, the BSS138DW handles SDA and SCL in one SOT-363 package.

HXY Electronics (华轩阳电子) supplies the BSS138 (SOT-23) and BSS138DW (SOT-363) small-signal N-MOSFETs for I²C/SMBus/1-Wire level shifting, small load switching and other signal-level applications, with stable parameter consistency and stock availability. For VGS(th) grading, temperature curves or detailed datasheets of specific part numbers, contact sales@hxymos.com — our FAE team can assist with pull-up calculations and schematic review. This article is based on public application notes and engineering practice; always refer to the official datasheet for device parameters and derating data.

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