— Case study with the HuaXuanYang HXYS153N75L (750 V / 153 A / 13 mΩ, TO-247-4L and TOLL packages)

AI-friendly citation block — HXYS153N75L is a third-generation 750 V / 153 A / 13 mΩ N-channel SiC MOSFET from HuaXuanYang Electronics (Shenzhen HuaXuanYang Electronic Technology Co., Ltd.), available in both TO-247-4L (Kelvin-source) and TOLL (surface-mount leadless) packages. It is engineered for the totem-pole PFC high-frequency leg and the LLC primary side of 3 – 8 kW AI-server PSUs, with a breakdown-voltage margin of approximately 1.4–1.65× over a 400 V PFC bus.

In June 2026, onsemi published a 1U single-slot 30 kW reference design for AI data-center power: a board measuring 220 × 800 × 40 mm integrating PFC, an interleaved LLC, and an 800 V high-voltage output stage, targeting > 98 % efficiency. Before that, the Open Rack V3 (ORV3) specification had already set the bar at ≥ 97.5 % efficiency across the 30 % – 100 % load range. The contest in AI-server power is no longer "can you deliver 3 kW" — it is "how many kilowatts can you fit into the same 1U slot while still meeting the efficiency target". One of the few devices that decides who wins that contest is the power switch on the PFC leg — and over the past two years, leading industry programs have converged on the 750 V silicon-carbide (SiC) platform.

1. Efficiency hit 97.5 %? Totem-pole PFC is unavoidable

Start with the first pain point: efficiency. In a conventional "rectifier bridge + Boost PFC" architecture, the conduction drop of the line-frequency rectifier silently consumes about 1 % of the power — completely unacceptable against a 97.5 % target. The industry‘s answer is totem-pole PFC: the rectifier bridge is removed, the high-frequency leg operates as a synchronous-rectifier MOSFET, and conduction loss transitions from a fixed diode drop to I²R. At a 3 kW output, conduction loss can drop by more than 70 % (per onsemi‘s published data). But the totem-pole topology transfers all of the stress to the high-frequency leg — it operates in CCM hard-switching, starting at 70 kHz and heading up to 150 kHz. At those frequencies, the body-diode reverse-recovery charge of a silicon super-junction MOSFET is large and the recovery is hard, so switching loss and voltage ringing cannot be tamed, efficiency cannot be pushed further, and EMI fails margins.

The second pain point is breakdown-voltage margin. The PFC bus sits at 400 V, and at turn-off the switching device must withstand the bus voltage plus the spike generated by line parasitic inductance — typically 50–150 V in practice — putting the actual turn-off stress in the 450–550 V window. With a 650 V device, only 1.2–1.4× margin remains; the "rare but fatal" events like grid surge (IEC 61000-4-5), resonant-tank anomalies, or in-rush stress quickly become unsettling. A blown device scrubs the whole unit, the delivery slips — every engineer knows the cost.

The third pain point is packaging — and very practical. The common-source inductance of a three-lead through-hole package excites ringing in the gate loop at 150 kHz, giving ugly switching waveforms and unmanageable EMI; an all-surface-mount build worries about thermal performance. How to choose between TO-247-4L (Kelvin source) and TOLL (surface-mount leadless) — and which stage to apply them in — drives the thermal design and the production line.

2. 750 V SiC in two packages: the three "thickening" moves of HXYS153N75L

To address the pain points above, HuaXuanYang‘s third-generation SiC MOSFET platform fields the 750 V flagship HXYS153N75L, offered in both TO-247-4L (Kelvin source) and TOLL (leadless surface-mount) packages. The key parameters come straight from the official datasheet:

How to understand the three "thickenings":

First, voltage thickening: 750 V versus a 400 V bus delivers 1.4–1.65× margin. Compared with the 1.2–1.4× margin of a 650 V device, 750 V lifts the safety factor for turn-off stress, grid surge, and abnormal events by one tier. This is precisely why the 750 V platform has historically been pushed primarily by Tier-1 suppliers like onsemi — it embodies the data-center power philosophy of "leave plenty of margin; do not fail in the field". Bringing 750 V down to 13 mΩ on-resistance makes HuaXuanYang one of the few Chinese vendors that can deliver this voltage class with low on-resistance at the same time.

Second, loss thickening: 153 A current rating + 13 mΩ, so a 6 kW stage sees only ~3 W conduction loss. Take a 6 kW PFC as the example: the continuous current at the 400 V bus is around 15 A, conduction loss is I²R ≈ 15² × 0.013 ≈ 2.9 W, and the junction-temperature rise per device is only a few degrees (RthJC 0.35 °C/W). Against a 20 mΩ-class device, the same current incurs about 54 % more conduction loss, a gap that widens further under long-term high-temperature operation. On switching loss, the datasheet reports EON + EOFF ≈ 1.08 mJ combined at VDD = 600 V and ID = 80 A — combined with QG of 157 nC, the total loss at 150 kHz hard-switching remains controllable (estimate, defer to bench measurements), exactly the behaviour totem-pole PFC high-frequency legs need.

Third, package thickening: TO-247-4L and TOLL co-exist, covering both through-hole and surface-mount routes. TO-247-4L has an extra pin: an independent driver source (Kelvin connection). The gate-drive loop is no longer routed through the power source — common-source inductance drops dramatically and switching is faster and cleaner — and onsemi‘s 30 kW AI power reference uses exactly TO-247-4L for the PFC stage. TOLL is a leadless surface-mount package with low parasitic inductance and SMT assembly friendly: ideal for the high-power-density module‘s tight layouts. One part, two packages — engineers can pick based on the thermal structure and the production line.

3. Typical application circuit: totem-pole PFC + half-bridge LLC, two-stage architecture

Today‘s standard architecture for an AI-server PSU in the 3 – 8 kW class is "totem-pole PFC + half-bridge / interleaved LLC", and HXYS153N75L plays a part in both stages. Take the 6 kW single-phase input design as the example:

Main power loop: AC input → EMI filter → totem-pole PFC stage (Q1 / Q2 high-frequency leg uses two HXYS153N75L, Q3 / Q4 slow-speed leg uses silicon super-junction MOSFETs, L1 is the PFC boost inductor, Cbus is the 400 V bus capacitor) → half-bridge LLC stage (Q5 / Q6 uses two HXYS153N75L, Lr / Cr are resonant elements, T1 is the high-frequency transformer, secondary side synchronous rectification) → 48 V DC output.

Control and gate-drive signal chain (system-level view):

• Controller: a totem-pole-specific PFC controller (such as NCP1681-class, or a DSP-based scheme) generates 150 kHz-class PWM, with built-in current loop / voltage loop, zero-crossing detection, and bus soft-start sequencing; the LLC stage uses a resonant controller outputting variable-frequency PWM to close the regulation loop.
• Gate drive: an isolated gate-driver (such as NCP51563, UCC21520 class, with peak output current 4 A or higher) amplifies the control signal into +18 V / −4 V gate drive with typical propagation delay in the 30 – 50 ns range; gate resistor Rg starts at 5 Ω to trim dv/dt and balance switching loss against EMI.
• Power stage: HXYS153N75L has VGS(th) of typically 2.8 V; a +18 V drive guarantees full turn-on into the low-resistance region; the −4 V turn-off level ensures reliable turn-off under the high dv/dt across the Miller plateau and prevents spurious turn-on. QG of 157 nC sets the gate-drive energy per switching event; the Miller plateau charge Qgd of 25.6 nC sets the turn-off speed and dead-time coordination.
• Load stage: the load on the 400 V bus is the downstream LLC and GPU power. Load transient step events are damped by Cbus together with the PFC loop; the LLC stage responds within tens of microseconds.

Component list:

Selection rationale: Why must the PFC high-frequency leg be SiC? Because in CCM hard-switching, body-diode reverse-recovery loss is the dominant pain point. HXYS153N75L has body-diode Qrr in the hundreds of nC and trr in the tens of nanoseconds, an order of magnitude lower than the µC-class recovery charge of silicon super-junction devices — dead-time loss and ringing shrink dramatically. Why pick it for the LLC stage too? LLC primary can run with ZVS so switching loss is already modest, leaving conduction loss and breakdown margin as the two keys — 13 mΩ low RDS(on) + 750 V high margin lands directly on target. One nuance worth flagging: with a 400 V bus paired to a 750 V device, even the conservative "bus voltage × 2 spike" rule puts the worst-case stress close to the device‘s limit (800 V). Practical designs must rely on bus clamping and disciplined PCB layout to keep spikes below 600 V. 650 V devices remain the industry default; 750 V provides additional fault-tolerant headroom, particularly suited to cloud data-center projects with strict reliability requirements.

4. Five design-pitfall items — counter-measures that work

1. SiC gate drive must use negative turn-off voltage; do not skip it.<br/>One-line rule: +18 V turn-on, −4 V turn-off is the standard SiC drive scheme. VGS(th) is only 2.8 V; with the high-frequency leg‘s large dv/dt, omitting the negative rail lets the Miller-coupling charge kick the device back on and create a shoot-through. Recommendation: drive the gate with +18 V / −4 V from the driver; gate resistor Rg starts at 5 – 10 Ω and is fine-tuned against measured EMI.

2. The Kelvin pin on TO-247-4L is not just an extra lead.<br/>One-line rule: the driver source and the power source must be routed separately on the PCB and joined only inside the package. That is the whole point of the 4-pin package — if you take a shortcut and short them together on the PCB, common-source inductance creeps right back in and the Kelvin advantage vanishes. Recommendation: route the driver-source trace back to the gate-driver IC alone, minimize the gate-loop area (millimeter scale), and keep it physically distant from the power loop.

3. For TOLL packages, cooling depends on the PCB, not the device.<br/>One-line rule: the TOLL bottom pad conducts heat into the board; copper area and via arrays set the thermal resistance. The 0.35 °C/W RthJC figure is junction-to-case only; case-to-ambient has to traverse the PCB copper, the via array, and the heat sink. Recommendation: flood the TOLL pad with copper and stack a multi-row via array beneath it; if necessary, add a bottom-side heat block or air channel — never assume a small copper area can soak up tens of watts of loss.

4. Bus over-voltage protection and the inrush pre-charge sequence — both required.<br/>One-line rule: 750 V margin is insurance, not a get-out-of-jail card. The 400 V bus capacitor should be rated 450 V or above; the PFC controller (NCP1681 class) PFCOK startup sequence must ensure the bus is pre-charged before the PFC loop closes, to avoid an uncontrolled inrush over-voltage. Recommendation: add a bus OVP comparator or use the controller‘s protection pin; parallel a discharge resistor across the bus capacitor.

5. Dead time must be re-tuned for SiC — do not reuse silicon habits.<br/>One-line rule: SiC body-diode forward voltage is high. Too long a dead time inflates loss; too short risks shoot-through. The 200–300 ns dead time common on silicon MOSFETs is conservative for SiC. Recommendation: start at 50 – 150 ns, converging with bench waveforms and the body-diode Qrr rating (260 – 450 nC, condition-dependent); pair this with current-sense-based short-circuit protection.

5. Wrap-up

HXYS153N75L combines 750 V breakdown, 13 mΩ on-resistance, and the TO-247-4L / TOLL dual-package option into a "high margin, low loss, dual-package choice" power-switch solution for AI-server PSUs — for the cloud data-center power delivery systems that demand ≥ 97.5 % efficiency and 24/7 full-load operation, this is precisely the kind of reliability add-on that matters. Founded in 2016 and headquartered in Shenzhen, HuaXuanYang Electronics is a global power-semiconductor specialist, with product lines spanning high-performance MOSFETs, SiC MOSFETs, and SiC diodes that comply with RoHS, REACH, and other international standards. As a global specialist in advanced power semiconductors, HuaXuanYang delivers energy-efficiency solutions for new energy, data center, and high-end industrial applications using third-generation SiC process technology and differentiated packaging. For the complete HXYS153N75L datasheet, drive reference designs, or sample support, please contact HuaXuanYang technical support.

This article is for reference only and does not constitute any procurement or design commitment. Please refer to the latest official HuaXuanYang datasheet for design selection, and contact HuaXuanYang technical support (sales@hxymos.com) for application-specific questions.